1. Field of the Invention
The present invention generally relates to high density CMOS FET devices and integrated circuits, and the fabrication of such, and, in particular, to high density CMOS FETs having residual defects particularly associated with source and drain regions formed in a multiple retrograde doping profile well structure that essentially eliminates the occurrence of latch-up during operation.
2. Description of the Prior Art
Reduction of feature size (scaling) is necessary for the application of CMOS FET devices to VLSI integrated circuits. Scaled, and therefore high density, CMOS devices are plagued by a condition known as latch-up. Encountered during operation, latch-up is characterized as a high current condition wherein the device is irreversibly latched into a single electrical state typically preventing the entire circuit from functioning properly and resulting in device damage, if not complete destruction.
The latch-up condition is generally attributed to the presence and undesirable function of parasitic bipolar transistors inherently formed in the CMOS FET structure. The configuration of the parasitic bipolar transistors is such that a closed loop feedback path typically having a gain greater than one exists. Thus, when random, atypical operational conditions are encountered, such as electrical transients, regenerative feedback occurs with a resultant latch-up of the device's electrical state.
CMOS latch-up is a commonly recognized problem. See, for example, "The Physics and Modeling of Latch-up in CMOS Integrated Circuits," D. B. Estreich, Technical Report No. G-201-9, prepared under Defense Advanced Research Projects Agency Contract No. DAAG-07-C-2684, November 1980; summarized in "Modeling Latch-up in CMOS Integrated Circuits", D. B. Estreich and R. W. Dutton, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. CAD-1, No. 4, October 1982, pp. 157-162; "A Retrograde P-Well for Higher Density CMOS", R. D. Rung et al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 10, October 1981, pp. 1115-1119; "Method for Radiation Hardening Semiconductor Devices and Integrated Circuits to Latch-Up Effects", U.S. Pat. No. 4,318,750; and "Silicon-Gate C-MOS Chips Gain Immunity to SCR Latch-up", L. Walneman, Electronics, Vol 56, No. 16, Aug. 11, 1983, pp. 136-140.
Correspondingly, a large variety of methods of reducing the parasitic loop gain have been proposed. These include, most notably, the provision of parasitic-current blocking or shorting guard-ring structures interposed between the complementary PMOS and NMOS FET transistors of the CMOS device, utilizing a deep peak or retrograde doping profile well region, irradiation of the CMOS device with high energy particles such as neutrons and protons, and provision of low resistivity buried layers in the CMOS structure. However, these methods are variously disadvantageous due to substantially increased device structure and fabrication process complexity, low degrees of reproducibility, excessive degradation of device's operating characteristics including substantially increased leakage currents, and, in particular, failure to reduce the parasitic feedback loop gain to less than one.